Rspress

# #hbUCPBackend

`#define HB_UCP_CORE_ANY (0 << 0) #define HB_UCP_BPU_CORE_0 (1ULL << 0) #define HB_UCP_BPU_CORE_1 (1ULL << 1) #define HB_UCP_BPU_CORE_2 (1ULL << 2) #define HB_UCP_BPU_CORE_3 (1ULL << 3) #define HB_UCP_BPU_CORE_ANY (1ULL << 7)`

- Member

  Member Name | Description
  --- | ---
  `HB_UCP_CORE_ANY` | Arbitrary executable hardware on Soc.
  `HB_UCP_BPU_CORE_0` | BPU core 0.
  `HB_UCP_BPU_CORE_1` | BPU core 1.
  `HB_UCP_BPU_CORE_2` | BPU core 2.
  `HB_UCP_BPU_CORE_3` | BPU core 3.
  `HB_UCP_BPU_CORE_ANY` | Arbitrary BPU core.

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